The present invention relates generally to a semiconductor device, and more particularly, to a technology for adjusting a setup time and a hold time using external manipulation such as fuse cutting.
A latch circuit refers to a circuit that maintains a signal inputted to a semiconductor device for a given period of time.
FIG. 1 is a circuit diagram showing an input latch circuit according to the conventional art. FIG. 2 is a timing diagram illustrating the operation of the input latch circuit shown in FIG. 1.
The input latch circuit according to the conventional art comprises a plurality of PMOS transistors P10˜P14, a plurality of NMOS transistors N11˜N15, and inverters I11 and I12.
The latch circuit performs a latch operation according to an input signal LAT_IN and a clock signal CLK. FIG. 2 illustrates how the latch circuit is synchronized with respect to a rising edge of the clock signal CLK to latch the input signal LAT_IN.
The input signal LAT_IN transits to a high level when the clock signal CLK is at a low level. The PMOS transistors P11, P14, P12 and the NMOS transistors N11, N12, N14 are turned on so that nodes LAT1, LAT1B are at a high level.
While the input signal LAT_IN maintains the high level, the clock signal CLK transits to a high level. The NMOS transistor N15 is then turned on so that the node LAT1 transits to a low level. As a result, an output signal LAT_OUT is outputted and maintains a high level. The PMOS transistor P12 is turned on so that the node LAT1B maintains the high level. The PMOS transistor P13 is turned off.
The input signal LAT_IN and the clock signal CLK then transit to a low level. The PMOS transistor P14 is turned on to transit the node LAT1 to a high level. As a result, the output signal LAT_OUT is transits to a low level. The PMOS transistor P11 is then turned on to maintain the node LAT1B at the high level.
As shown in FIG. 2, the latch circuit receives data using the clock signal CLK and requires receiving a signal before the clock signal CLK transits levels. Even after a phase of the clock signal CLK changes, the signal input must continue for a given period of time.
A setup time (Ts) refers to a time period in which a signal must be inputted before the clock signal CLK transits levels. A hold time (Th) refers to a time period during which the signal input is maintained after the clock signal CLK transits levels.
If the setup time and the hold time are not maintained for a given time in the latch circuit, the input data is not latched an error is generated as a result. Accordingly, the setup time and the hold time must be properly adjusted when they are incorrectly set. In order to adjust the setup time and the hold time, the structure of the circuit supplying the input signal LAT_IN and the clock signal CLK to the latch circuit must be changed in the conventional semiconductor device.
However, if the circuit is changed, a great deal of time is required until the circuit may be applied to a final wafer. As a result, it takes a large amount of time to develop a device.